1. Field of the Invention
The present invention relates to the field of digital computation circuits. More particularly, the present invention relates to an architecture for integrated circuit logic elements performing arithmetic operations.
2. Description of the Prior Art
It is fundamental to the operations of many electronic systems as well as processors to support digital (i.e., binary) addition of at least two digital inputs. For example, processors normally employ integrated circuits which perform various arithmetic or logical ("bitwise") operations on multiple digital inputs in order to produce digital sums and other logical functions. These integrated circuits may include an address generation unit ("AGU") for performing memory loads and data storage; a branch address calculator ("BAC") for calculating appropriate branch instructions and the like.
Referring to FIG. 1, in conventional x86 Intel.RTM. Microprocessor Architecture, the AGU employs integrated logic to produce an effective address ("EFF.sub.-- ADDR") and a linear address ("LIN.sub.-- ADDR"), both of which have an arbitrary bit length "n" and are well known in the art. This logic is referred to as a "generation unit" 100 which includes a well known digital adder such as a carry-save-adder ("CSA") 110, operating in series with conventional adders 120 and 130. The effective and linear addresses may be calculated by "adding" digital inputs by using a combination of CSAs and carry propagate adders in parallel. These digital inputs are referred to as a base address ("S1"), an index multiplied by any scaling factor ("S2"), a displacement ("S3") and a segment base ("S4") according to the following equations: EQU EFF.sub.-- ADDR=S1+S2+S3; and Eqn. 1 EQU LIN.sub.-- ADDR-S4+EFF.sub.-- ADDR, where Eqn. 2
"+" is an operator representing a normal arithmetic addition.
As shown in FIG. 1, the CSA 110 receives three digital inputs in parallel, identified above for convenience as "S1", "S2" and "S3", via communication lines 101, 102 and 103, respectively. Usually, these digital inputs "S1-S3" are 32-bit double words, but it is contemplated that they may be of any arbitrary bitwidth. After transferring digital inputs "S1-S3" into the CSA 110, the CSA 110 sums these digital inputs to produce a number of sum ("E.sub.-- SUM") signals via communication lines 111 and carry ("E.sub.-- CARRY") signals through communication lines 112. These E.sub.-- SUM and E.sub.-- CARRY signals are calculated by performing logical operations on corresponding bits of the digital inputs and may be represented through the following logical representations where "i" is an arbitrary bit number: EQU E.sub.-- SUM.sub.i =S1.sub.i XOR S2.sub.i XOR S3.sub.i ;
and EQU E.sub.-- CARRY.sub.i+1 =(S1.sub.i XNOR S2.sub.i) && S1.sub.i .vertline..vertline. (S1.sub.i XOR S2.sub.i) && S3.sub.i,
where:
".vertline. .vertline." is a bitwise logical OR, PA1 "&&" is a bitwise logical AND, and PA1 "XOR", "XNOR" are well known digital operations.
These E.sub.-- SUM and E.sub.-- CARRY signals, propagating through the communication lines 111 and 112, are input into a first conventional adder 120 to produce the effective address "EFF.sub.-- ADDR" via communication lines 121. The EFF.sub.-- ADDR propagates through the communication lines 121 to various components of the processor and is input into the second conventional adder 130 in combination with digital input "S4" propagating through communication lines 122. The EFF.sub.-- ADDR, in combination with the digital input "S4", produce the linear address "LIN.sub.-- ADDR" as defined above. The LIN.sub.-- ADDR propagates through communication lines 131 for use by the processor. However, as operational speed of the processor increases, this conventional architecture for calculating EFF.sub.-- ADDR and LIN.sub.-- ADDR has a number of disadvantages.
One disadvantage is that this architecture experiences a large amount of latency in producing both the effective and linear addresses due to its serial configuration. For processors requiring minimal latency and higher operating speeds, serial calculation of the linear addresses is not a viable option.
Another disadvantage is that extra loading is placed on the communication lines 121 providing the EFF.sub.-- ADDR since EFF.sub.-- ADDR is used in both the LIN.sub.-- ADDR addition and in other logical functions.
Thus, it would be advantageous to implement an integrated circuit producing both the effective address and the linear address in parallel which overcomes both of the above-identified disadvantages.